Design compiler change_names

Feb 19, 2016Hi,. I am using the following command to elaborate my design. The design name is updated with the parameter names and values.RTL compiler: Port names expansion of record types in vhdl synthesisDesign Compiler commands to RTL command ConversionMore results from community.cadence.com

Feb 19, 2016Hi,. I am using the following command to elaborate my design. The design name is updated with the parameter names and values.

How do I compile a VG design?

You will have to add the standard cell verilog modules as a file under analyze in order to compile your .vg design.
You can also compile your design within design_vision by loading file using the analyze menu and then using the same dc_compile script.
It will complain about the /* */ comments in the script file when run this way.

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